Memory ordering

Memory ordering describes the order of accesses to computer memory by a CPU. The term can refer either to the memory ordering generated by the compiler during compile time, or to the memory ordering generated by a CPU during runtime.

In modern microprocessors, memory ordering characterizes the CPUs ability to reorder memory operations - it is a type of out-of-order execution. Memory reordering can be used to fully utilize the bus-bandwidth of different types of memory such as caches and memory banks.

On most modern uniprocessors memory operations are not executed in the order specified by the program code. In single threaded programs all operations appear to have been executed in the order specified, with all out-of-order execution hidden to the programmer – however in multi-threaded environments (or when interfacing with other hardware via memory buses) this can lead to problems. To avoid problems memory barriers can be used in these cases.

Compile-time memory ordering

The compiler has some freedom to resort the order of operations during compile time. However this can lead to problems if the order of memory accesses is of importance.

Compile-time memory barrier implementation

See also: Memory barrier

These barriers prevent a compiler from reordering instructions during compile time – they do not prevent reordering by CPU during runtime.

asm volatile("" ::: "memory");

or even

__asm__ __volatile__ ("" ::: "memory");

forbids GCC compiler to reorder read and write commands around it.[1]


forbids the compiler to reorder read and write commands around it.[2]




Runtime memory ordering

In symmetric multiprocessing (SMP) microprocessor systems

There are several memory-consistency models for SMP systems:

On some CPUs

Memory ordering in some architectures[7][8]
Type Alpha ARMv7 PA-RISC POWER SPARC RMO SPARC PSO SPARC TSO x86 x86 oostore AMD64 IA-64 z/Architecture
Loads reordered after loads Y Y Y Y Y Y Y
Loads reordered after stores Y Y Y Y Y Y Y
Stores reordered after stores Y Y Y Y Y Y Y Y
Stores reordered after loads Y Y Y Y Y Y Y Y Y Y Y Y
Atomic reordered with loads Y Y Y Y Y
Atomic reordered with stores Y Y Y Y Y Y
Dependent loads reordered Y
Incoherent instruction cache pipeline Y Y Y Y Y Y Y Y Y

Some older x86 and AMD systems have weaker memory ordering[9]

SPARC memory ordering modes:

Hardware memory barrier implementation

See also: Memory barrier

Many architectures with SMP support have special hardware instruction for flushing reads and writes during runtime.

lfence (asm), void _mm_lfence(void)
sfence (asm), void _mm_sfence(void)[10]
mfence (asm), void _mm_mfence(void)[11]
sync (asm)
sync (asm)
mf (asm)
dcs (asm)
dmb (asm)
dsb (asm)
isb (asm)

Compiler support for hardware memory barriers

Some compilers support builtins that emit hardware memory barrier instructions:

See also


  1. GCC compiler-gcc.h
  2. ECC compiler-intel.h
  3. Intel(R) C++ Compiler Intrinsics Reference
    Creates a barrier across which the compiler will not schedule any data access instruction. The compiler may allocate local data in registers across a memory barrier, but not global data.
  4. Visual C++ Language Reference _ReadWriteBarrier
  5. Reordering on an Alpha processor by Kourosh Gharachorloo
  6. Memory Ordering in Modern Microprocessors by Paul McKenney
  7. Memory Barriers: a Hardware View for Software Hackers, Figure 5 on Page 16
  8. Table 1. Summary of Memory Ordering, from "Memory Ordering in Modern Microprocessors, Part I"
  9. SFENCE Store Fence
  10. MFENCE Memory Fence
  11. Data Memory Barrier, Data Synchronization Barrier, and Instruction Synchronization Barrier.
  12. Atomic Builtins
  14. MemoryBarrier macro
  15. Handling Memory Ordering in Multithreaded Applications with Oracle Solaris Studio 12 Update 2: Part 2, Memory Barriers and Memory Fence

Further reading

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